Building RISC-V GPUs, one systolic array at a time.
focus
RTL development, CXL compute system architectures, and HW/SW co-design.
Current quests
Which tracks am I actively publishing about?
- Tiny TPU — a fully FPGA-resident systolic array for RISC-V-adjacent matrix compute, running on real hardware.
- Prosperity PPU: an SNN accelerator exploiting product sparsity via a TCAM-based pattern-reuse detector.
- CXL-accelerated inference: memory-pooled architectures for low-latency LLM serving.
Also writing
A complete, start-to-finish reference on computer architecture — memory hierarchies, prefetchers, CXL, the whole stack, written as I learn it in public. comparch.5iri.me →
Latest writing
blog · 2026-08-22
How Wrong Can Taylor Be Before It Stops Being Right?
A bad cube-root approximation sent me down a rabbit hole about when Taylor can get the numbers wrong but the comparison right.
blog · 2026-08-19
From x != 0 to a Waveform
my gsoc 2026 work on CIRCT, teaching circt-bmc to explain itself
blog · 2026-05-25
The Work Got More Real
On sitting in the messy middle of unfinished projects, tiny TPU work getting more real, and starting final year.
About
I'm Shri, 20, final-year engineering student. I like watching silicon go from an idea to something that actually toggles — RTL by day, Red Bull, chips, and cat memes by night.
Contact
Reply speed depends on how the RTL is behaving that week.
Hobbies
Off the clock, mostly.
- I love mathematics! I try to sit down and work on some problems whenever I can! current progress in abstract algebra notes at this page
- I love listening to music!! Here's my spotify :)
- revamp my website for the 1000th time.
